虚拟寄存器结构

THE VIRTUAL REGISTER ARCHITECTURE

虚拟存储器概念在计算机体系结构中已经沿用近３０年．鉴于面向寄存器的ＲＩＳＣ结构的迅速发展以及寄存器结构对指令级并行性的重要性，本文首先提出了虚拟寄存器的新概念．虚拟寄存器结构是指令级并行调度和发射ＴｒａｃｅＭｅｒｇｉｎｇ算法在处理机体系结构上的一种实现方法．虚拟寄存器结构使得基本块之间的寄存器相关性得到消除，并提高了ＲＩＳＣ结构中的寄存器使用效率，使得ＴｒａｃｅＭｅｒｇｉｎｇ算法得以实现．本文采用高级语言编译器和程序驱动仿真，对虚拟寄存器结构进行了定量的分析，并与ＶＬＩＷ结构上的ＴｒａｃｅＳｃｈｅｄｕｌｉｎｇ算法进行比较，从而验证了ＴｒａｃｅＭｅｒｇｉｎｇ算法的效果，并进一步考察了虚拟寄存器的数量和使用效率的关系．

This paper presents a new concept of virtual register. Virtual register architecture is an implementation approach of ILP scheduling and Trace Merging algorithm of instruction issue in processor architecture. Virtual register architecture could eliminate most cases of register dependencies between basic blocks, could increase the efficiency of register usage and implement the Trace Merging Algorithm.This paper employs high-level language compiler and program-driven simulation to give a quantitative analysis of virtual-register structure, and to compare with the Trace-Scheduling algorithm in VLIW structure. The result of verification for Trace-Merging Algorithm and the further study of relationship between the quantity and efficiency of virtual register are given.