基于FPGA的开关盒互连容错算法的研究

Research of Interconnect Fault Tolerance of Switch Blocks in FPGA

FPGA主要由两个基本部分组成,一是可配置逻辑部件,另一部分就是互联网络,负责对可配置逻辑块间的通信。FPGA内部大约80%的晶体管都是作为可编程开关和缓冲器来完成可编程路由网络工作的。文中主要对出现错误的开关盒阵列中可执行的路径数量进行评估,并且使用算法找到合适的路径,避开错误。

The FPGA mainly has two basic parts, one is configurable logic blocks, the other is the interconnection network, it is responsible for communication in CLBs. Over 80% of transistors inside the FPGA are dedicated to the programmable routing network as programmable switches and buffers. The main objective of this paper is to assess the routability of the switch block array in the presence of faults, and to use algorithm to find appropriate route, to avoid fault.