基于FPGA组的ASIC验证原型系统和逻辑分割算法的研究与实现

Research and Implementation of the ASIC Verification Prototype and Logic Partitioning Algorithms Based on FPGAs

随着ASIC设计规模的增长和问题复杂度的增加,传统的逻辑验证方法已难以满足应用的要求。基于FPGA组的验证方法能有效缩短系统的开发周期,可提供更快、更彻底的验证,更能满足逻辑验证的需要。本文对验证系统的可配置互连结构和ASIC逻辑分割算法进行了研究,提出了相应的实现方法。

With the rapid growth of the ASIC design size and complexity, traditional verification approaches can hardly meet the emerging requirements. A new ASIC verification approach based on FPGAs can shorten the development cycle efficiently, implement verification more quickly and completely and satisfy the requirements of ASIC verification better. This paper discusses the reconfigurable interconnection structure of prototype systems, presents a partitioning algorithm, and gives the corresponding imolementation.