Garfield 5微处理器芯片的电源网络和面积优化

Optimization of Power Network and Area of the System Chip Garfield5

深亚微米的集成电路设计中,芯片的面积与成本是紧密相连的。随着芯片的面积增大,其制造成本不断增加,但芯片成品率却急剧下降。因此在后端版图设计中,设计人员的目标之一就是应尽可能减小芯片的面积。本文介绍了Garfield5系统芯片的版图设计中,如何利用Synopsys公司的后端设计工具Astro,在布局布线等各个步骤中对芯片面积和电源网络进行设计和优化,并成功实现典型情况下的125MHz时钟频率、5.0mm×5.0mm以内的芯片面积。

When SoC design goes into Deep-Submicrometer era, the chip area is much relative to the product cost. As the area of chip increases, the cost of chip manufacturing becomes more expensive and the successful chip manufacturing rate reduces. Thus decreasing the area of chip is one of the most critical challenge to the IC backend designers. This article introduces how to use the Astro （backend design tool provided by Synopsys） to do the optimization of chip area and power network of the system chip Garfield 5. It achieves the 125MHz at typical case, and chip area within 5.0 mm× 5.0 mm.