MIMO-OFDM系统定时同步算法的FPGA设计

FPGA Design of Timing Synchronization in MIMO-OFDM System

对多入多出-正交频分复用(MIMO-OFDM)系统中基于训练序列的定时同步算法进行了阐述.着眼于系统定时同步算法的硬件实现,对通过现场可编程门阵列(FPGA)实现定时同步算法的复杂度按照单位时间内乘、加次数的方法进行了分析.为降低系统中定时同步算法在FPGA实现过程中的复杂度,对单个定时同步模块内部子模块,以及多个定时同步模块间的关系进行了研究,提出了MIMO-OFDM系统定时同步算法的简化实现方案,并对简化方案在Xilinx公司的Virtex-ⅡPro系列FPGA中的资源使用情况进行了统计.研究表明,简化实现方案可以用于MIMO-OFDM系统定时同步算法的硬件实现.

Timing synchronization algorithm based on training sequence in multi-input multi-output-orthogonal frequency division multiplexing （MIMO-OFDM） system were demonstrated. With a view to hardware implementation of timing synchronization algorithm in MIMO-OFDM system, the complexity of timing synchronization algorithm implementation with field programmable gate array（FPGA） was analyzed according to multiplying and adding frequency in unit time. To make the timing synchronization algorithm in MIMO-OFDM system less complicated during FPGA implementation, after study on sub-modules in individual timing synchronizing module and relationship among multiple timing synchronizing modules, a simplified implementation scheme for MIMO-OFDM system timing synchronization algorithm was brought forward, and statistics on resource occupation of such a scheme in Virtex-Ⅱ Pro series FPGA of Xilinx Company was given. Study shows the simplified implementation scheme is applicable in hardware implementation of MIMO-OFDM system timing synchronization algorithm.