摘要
通过调整扫描链上扫描单元顺序与逻辑门插入相结合,以减少扫描移入阶段扫描链上不必要的状态跳变,从而达到降低测试中电路动态功耗的目的.在ISCAS’89基准电路上进行的实验表明,该方法最多能将扫描移入阶段峰值功耗降低94.5%,平均功耗降低93.8%,而面积开销可以忽略不计.
This paper proposes an approach to eliminate unnecessary transitions on scan chains during scan-in phase. By using scan cells reordering in combination with logic gate insertion, it reduces scan-in power dissipation. Experimental results on ISCAS'89 benchmark circuits show that the proposed approach can reduce peak power dissipation by 94.5 % during scan test and average power by 93.8 %, with ignorable area overhead.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2006年第9期1391-1396,共6页
Journal of Computer-Aided Design & Computer Graphics
基金
国家重点基础研究发展规划项目(2005CB321604)
国家自然科学基金(90207002)
中国科学院计算技术研究所基金(20056330
20056600-16)
关键词
可测试性设计
动态功耗
扫描链
design for testability
dynamic power dissipation
scan chain