摘要
研究不同衬底材料上共面波导(CPW)线的损耗特性。实验结果表明,采用低阻SOI(20Ω·cm)作衬底制作的共面波导线的损耗比在低阻硅(20Ω·cm)上制作的有明显减少;而采用低阻硅,并沉积1μmSiO2作衬底的CPW线损耗大大降低。采用高阻SOI(1000Ω·cm)制备的CPW线在2GHz损耗仅为0.13dB/mm;通过在低阻硅上采用地屏蔽技术也可以有效地改善传输线的损耗特性,在整个频段内的损耗可与高阻SOI硅衬底上相比拟。
The transmission loss properties of different substrates are investigated systematically in this paper. The experiment results show that the attenuation of the CPW line on low resistivity SOI(20 Ω·cm)is much lower than that made directly on the low-resistivity silicon(20Ω· cm), and the loss on silicon with 1μm SiO2 can be reduced greatly. The attenuation for the CPW at 2 GHz is only 0.13 dB/mm on high resistivity SOI (1 000Ω·cm). The loss of the transmission lines is reduced effectively with shield ground on the low-resistivity silicon, which is comparable to the result of high resistivity SOI.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2006年第3期321-324,共4页
Research & Progress of SSE
基金
中科院重大项目
上海市重大项目资助(批准号:021111122)