摘要
提出了一种高速、可变长点、混合基8/4/2、浮点的FFT硬件模块化设计方案。设计方案中,改进了基8/4/2混合基算法,能够处理可变长2N(3≤N≤12)采样点;提出了一种乒乓RAM结构和数据地址的组织,可以同时存、取和处理16个数据,保证处理实时性;采用了超长流水线浮点执行单元,提高了处理结果的精度。目前,该设计已在FPGA上实现,采样点长4k时处理能力为250MSPS。采用0.18μmCMOS工艺综合,4k点时处理能力可达到800MSPS。
A novel method is proposes to design a configurable, mixed-Radix8/4/2 and floating-point high-speed FFT processor, The improved mixed-Radix8/4/2 algorithm, ping-pong RAM architecture, data address generator and pipelining floating-point process unit which enhance the processor＇s performance to read, write, compute 16 data simultaneously and process unfixed point with high-precision are discussed in detail. The design has been verified on the FPGA platform and synthesized in 0.18μm CMOS technology. It is showed that the IO rate is 250MSPS at 4k point and will reach to 800MSPS after its migration to ASIC.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2006年第17期254-256,282,共4页
Computer Engineering
基金
上海市科委科技发展基金资助项目(037062022)
关键词
混合基
乒乓RAM
浮点执行单元
流水线
Mixed-Radix
Ping-pong RAM
Floating-point process unit
Pipelining
