一种新型结构的高速时钟数据恢复电路

A New Architecture High Speed Clock and Data Recovery Circuit

针对高速(Gb/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路.该电路结构结合鉴频器和半速率二进制鉴相器,实现了频率锁定环路和相位恢复环路的同时工作.电路采用1.8 V,0.18μmCMOS工艺流片验证,面积约0.5 mm2,测试结果显示在2 Gb/s伪随机数序列输入情况下,电路能正确恢复出时钟和数据,核心功耗约为53.6 mW,输出驱动电路功耗约64.5 mW,恢复出的时钟抖动峰峰值为45 ps,均方根抖动为9.636 ps.

A new hybrid high speed clock and data recovery circuit suitable for the application in Giga bit/s serial data communication is presented. By adopting a frequency detector in parallel with a half-rate bang-bang phase detector, cooperation of the frequency locked loop and the phase locked loop is realized. Implement in a 1.8 V 0.18/an 1P6M standard CMOS process, the area of the circuit is 0.5 mm^2. Test results show that, with a 2 Gb/s PRBS input, the system can recover the data and clock correctly, the core power dissipation is 53.6 mW, the output buffer consumes 64.5 mW. The recovered clock has a 9. 636 ps and 45 ps RMS jitter and peak-peak jitter respectively.