一种I^2C总线快速收发器设计

Fast Mode I^2C Bus Receiver Design

I2C总线是飞利浦公司在1992年推出的芯片间互连的双向串行总线标准,与传统的并行连接相比,他具有只需要2根连接线,使用统一的串行协议来实现寻址与数据传递。I2C总线收发器的难点主要在于低噪声、低功耗和标准兼容性,本文描述了I2C总线收发器的设计,包括电路设计、版图设计以及模拟结果。Spice仿真结果表明该总线收发器达到了I2C标准要求。

I^2C bus is developed for interconnection between various chips in 1992. Compared with parallel interconnection, it has several advantages ; only need two wires,uniform serial protocol for address and data. It is difficult to design a low power, low noise I^2C receiver. A fast mode I^2C bus receiver is designed in this article, which including circuit design, layout and simulation results. Simulation results with Spice demonstrate that it is compliant with I^2C fast mode standard.