半导体封装测试系统的生产能力规划

Capacity Planning in Semiconductor Assembly and Test Manufacturing System

半导体封装测试生产线的流程复杂,资源多样。其生产能力规划需要解决生产任务在多个工厂的分配,资源在各个工厂优化安排的问题。当生产能力不足时,还需对如何优化地购进资源进行决策。文章介绍了半导体封装测试生产能力规划需要考虑的各个环节,提出生产过程模型单元(PPM)思想,建立了具有流程适应性的线性规划模型,解决了生产能力分配问题。在前一个问题求解结果基础上,还采用派生模型解决了制定资源购进计划的问题。模型已经成功应用在In tel公司的封装测试生产线上,与原来采用的电子表格的能力规划方法比较:实现了计划制订的自动化;规划时间从原来的22小时降低到目前的2小时;资源的优化分配方案帮助减少了资源的购买量,已为企业节约成本约240万美元。

Semiconductor assembly and test manufacturing is highly complex with intricate processes and resources. The capacity planning is involved in many problems including demand distribution to multi-factories, resource optimization and allocation for single factory, and resource purchase planning when capacity shortage occurs. For solving these problems, this paper firstly describes the details of main points in semiconductor assemble and test line capacity planning process, then proposes the process insensitive linear programming model which takes the concept of ＂production process model＂（PPM） and solves the capacity allocation problems. Based on the result of the former model, another derived model is constructed for setting resource purchase planning . The models have been successfully applied on Intel＇s Assemble and Test production line. As a result, the time of capacity planning has decreased from 22 hours with the original method using spreadsheets to 2 hours at present. At the same time, 2.4 million dollars have been saved for Intel factories by using this optimized resource allocation method.