摘要
文中研究JPEG2000标准中自适应算术编码器的硬件实现问题,采用并行结构的FPGA设计,并用Modelsimse5.8对其作仿真验证。设计使用VerilogHDL语言在RTL级描述,并以Xilinx VertexII系列中的xc2v250-6fg256器件为基础在ISE6.1下完成综合。
FPGA implementation of the adaptive arithmetic encoder in JPEG2000 standard is investigated. A parallel architecture is presented, which is simulated and verified with Modelsimse5.8 on FPC-A. The design is described with VerilogHDL at RTL level. Based on Xilinx VertexII xc2v250- 6fg256, synthesis are conducted with ISE6.1.
出处
《计算机技术与发展》
2006年第10期211-213,216,共4页
Computer Technology and Development
