低功耗CMOS同或门的设计

A Design of Low Power Consumption CMOS XNOR Gate

讨论了现有异或门/同或(XOR/XNOR)门的设计,指出了基于不同逻辑类型设计的门电路的优缺点.考虑到基于CMOS设计的XNOR门相对于其他逻辑门在各方面的优点,重点分析了CMOS XNOR门结构对门电路性能的影响.提出了一个新颖的CMOS同或门电路.经PSPICE仿真模拟表明,新设计在没有增加管子数的前提下,改善了门电路的性能.将新设计应用到全加器的设计中,其功耗和功耗延迟积的改进分别达到了9.9%和11.6%.

The existing different XOR/XNOR gate designs are investigated, and the merits and weaknesses of the existing gate designs are analyzed. Considering CMOS XNOR＇s evident advantages when compared to other logical gates, the research work is mainly focused on analyzing how the structure of the CMOS XNOR affects the circuit performance. Based on the analysis, a novel CMOS gate is proposed. PSPICE simulation shows that, compared to the other designs, the performance of the proposed gate is improved without increasing transistor count. The proposed XNOR is applied in the full adder design, and the simulation demonstrates that power consumption of the new full adder design can be reduced by up to 9.9%, and correspondingly, the power-delay product is improved by up to 11.6% compared to the CMOS full adder.