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纳米级MOS器件中电子直接隧穿电流的研究 被引量：4

A Study on Direct Tunneling Currents in Nano-MOS Transistors
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摘要 文章从分析量子力学效应对纳米级MOS器件的影响出发,采用顺序隧穿理论和巴丁传输哈密顿方法,建立了纳米级MOS器件直接隧穿栅电流的计算模型。通过和实验数据的比较,证明了该模型的有效性。计算结果表明,在纳米级MOS器件中,采用SiO2作栅介质时,1.5 nm厚度是按比例缩小的极限。该计算模型还可以用于高介电常数栅介质和多层栅介质MOS器件的直接隧穿电流的计算。 Based on the analysis of quantum mechanics effects on nano-metal-oxide-semiconductor transistors （nano-MOST）, a model of direct tunneling currents is established using the sequential tunneling theory and Bardeen＇s transfer Hamiltonian formalism. A comparison of experimental data with calculation results indicates the effectiveness of this model in this work. It is shown that the oxide of nano-MOST can be scaled down to 1.5 nm. This model could also he used to calculate direct tunneling currents of MOST with high-k gate dielectrics or stacked gate dielectrics.
作者 杨红官 李晓阳 喻彪 戴大康
机构地区 湖南大学应用物理系
出处 《微电子学》 CAS CSCD 北大核心 2006年第5期634-637,共4页 Microelectronics
基金 湖南省青年骨干教师基金资助项目(521105237) 湖南大学自然科学基金资助项目(521101805)
关键词 器件物理 纳米级MOS器件 直接隧穿电流 顺序隧穿 Device physics Nano-MOS transistors Direct tunneling current Sequential tunneling
分类号 TN386.1 [电子电信—物理电子学]
  • 相关文献

参考文献11

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二级参考文献5

  • 1吴大维,范湘军,郭怀喜,张志宏,李世宁.PECVD法氮化硅薄膜的研究[J].材料科学与工程,1997,15(1):46-49. 被引量：9
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共引文献1

同被引文献14

  • 1陈震,向采兰.Si_3N_4栅MOS器件的隧穿电流模拟[J].微电子学,2002,32(6):428-430. 被引量：2
  • 2王伟,孙建平,顾宁.纳米级MOSFET隧穿栅电流量子模型[J].微电子学,2006,36(5):622-625. 被引量：1
  • 3MOMOSE H S, ONO M, YOSHITOMI T, et al. 1.5 nm direct-tunneling gate oxide Si MOSFET' s[J]. IEEE Trans Elec Dev, 1996, 43(8): 1233-1242.
  • 4LIU X Y, KANG J F, HAN R Q. Direct tunneling current model for MOS devices with ultra-thin oxide including quatization effect and polysilicon depletion effect[J]. Sol Sta Commu, 2003, 125(3-4): 219-223.
  • 5WILK G D, WALLACE R M, ANTHONY J M. High-k gate dielectrics: current status and materials properties considerations[J]. J Appl Phys, 2001, 89 (10): 5243-5275.
  • 6BUCHANAN D A. Scaling the gate dielectric: materials, integration and reliability[J]. IBM J Res Develop, 1999, 43(3): 245-264.
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  • 9YEO Y-C, KING T-J, HU C-M. Direct tunnelingleakage current and scalability of alternative gate dielectrics[J]. Appl Phys Lett, 2002, 81(11): 2091- 2093.
  • 10ALTOLAGUIRRE F A, KER M D. Power-rail ESD clamp circuit with diode-string ESD detection to overcome the gate leakage current in a 40-nm CMOS process [J]. IEEE Trans Elec Dev, 2013, 60(10): 3500-3507.

引证文献4

二级引证文献2

微电子学
2006年 第5期

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