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一种提高锁相环抖动测量精度的方法 被引量:1

A New Method for Improving Accuracy of PLL Jitter Measurement
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摘要 根据高速、高精度锁相环抖动测量的需要,提出了一种对抖动线性放大的方法。这种方法将ps级的抖动放大为一定脉宽的脉冲信号,然后再通过一些简单的测试电路,对放大后的脉冲信号进行测量。由于对原来的微小抖动进行了线性放大,从而极大地提高了抖动测量的精度。基于0.8μm CMOS工艺,采用MOSFET LEVEL=2模型,对结论进行了SPICE仿真验证。 A method to amplify the small jitter linearly is presented, which makes the jitter much easier tor measurement. After amplification of the jitter, a corresponding pulse is transfered. As a result, the measurement accuracy is greatly improved. This method also provides a reference for measurement of high speed PLL' s. The results are verified using SPICE simulation based on 0.8μm CMOS process and MOSFET LEVEL=2 model.
出处 《微电子学》 CAS CSCD 北大核心 2006年第5期646-650,共5页 Microelectronics
基金 国家自然科学基金资助项目(90207018 60576030)
关键词 锁相环 抖动 内建自测试 Phase locked loop Jitter Built-in self-test
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参考文献7

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同被引文献6

  • 1BEST R E.锁相环设计、仿真与应用[M].李永明,译.北京:清华大学出版社,2007:272-280.
  • 2GRAY P R,HURST P J.Analysis and design of analog integrated circuits[M].北京:高等教育出版社,2005:708-716.
  • 3HASTIONS A.Theart of analog layout[M].北京:电子工业出版社,2006:459-461.
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  • 5JOHNS D A,MARTIN K.模拟集成电路设计[M].曾朝阳,赵阳,等译.北京:机械工业出版社,2005,223-224.
  • 6徐勇,赵斐,徐志军.一种宽电源锁相环电路的设计与实现[J].微电子学,2004,34(3):334-336. 被引量:1

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