一种3.3V 9位50 MS/s CMOS流水线A/D转换器

A 3.3V 9-Bit 50 MS/s CMOS Pipeline Analog-to-Digital Converter

设计了一种3.3 V 9位50 MS/s CMOS流水线A/D转换器。该A/D转换器电路采用1.5位/级,8级流水线结构。相邻级交替工作,各级产生的数据汇总至数字纠错电路,经数字纠错电路输出9位数字值。仿真结果表明,A/D转换器的输出有效位数(ENOB)为8.712位,信噪比(SNR)为54.624 dB,INL小于1 LSB,DNL小于0.6 LSB,芯片面积0.37 mm2,功耗仅为82 mW。

A 3.3 V, 9-bit, 50 MS/s pipeline analog-to-digital converter （ADC） is presented, in which an 8-stage （1.5-bit/stage） pipelining architecture is adopted. Each stage resolved two bits and the resulting 16 bits are combined with digital correction to yield 9 bits at the output of the ADC. Simulation results show that the ADC achieved a signal-to-noise ratio of 54. 624 dB, maximum differential nonlinearity of 0. 6 LSB, maximum integral nonlinearity of 1 LSB, and an ENOB of 8. 712 bits with only 82 mW of power.