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1.6 GHz 24位4阶Σ-Δ小数分频频率合成器 被引量:2

A 1.6 GHz Fractional-N Frequency Synthesizer with a 24-b 4^(th)-Order Σ-Δ Modulator
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摘要 介绍了一种3 V 0.35μm BiCMOS工艺实现的1.6 GHz小数分频频率合成器。它采用新型的24位4阶Σ-Δ调制结构数字调制器,以减少频率合成器的带内相位噪声、锁定频率切换时间,在获得高达20 MHz鉴相频率的同时,能达到小于1 Hz的频率分辨率。仿真结果表明,它的锁定范围是1.615~1.675 GHz,环路带宽100 kHz,带内相位噪声低于-90 dBc/Hz,锁定频率切换时间小于25μs,可以很好地满足个人手持电话系统PHS标准的应用。该电路功耗为20 mW,芯片面积1.7 mm×0.8 mm,其中,Σ-Δ调制部分所占面积为1 mm×0.4 mm。 A 1.6 GHz ∑-△ fractionabn frequency synthesizer is presented, which is implemented in 3-V 0. 35-μm BiCMOS process. A novel 24-b fourth-order ∑-△ modulator is employed to achieve low in-band phase-noise, agile switching, and fine frequency resolution less than 1Hz with 20 MHz reference frequency has been achieved. Simulation results show that the proposed system has a rapid switching time of 25μs, which meets the requirements of the personal mobile system(PHS) standard. The synthesizer has a 1.8% frequency tuning range from 1. 615 GHz to 1. 645 GHz. It dissipates 20 mW of power and occupies an active area of 1.7 mm×0. 8 mm including 1 mm × 0. 4 mm∑-△ modulator.
出处 《微电子学》 CAS CSCD 北大核心 2006年第5期683-687,共5页 Microelectronics
关键词 ∑-△调制 小数分频 频率合成器 鉴频器 环路滤波器 ∑-△ modulat!on Fractional-n Frequency synthesizer Frequency detector Loop filter
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参考文献7

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同被引文献13

  • 1吕立明,冯雷,肖仕伟.小数分频频率合成器的计算机辅助设计[J].信息与电子工程,2006,4(5):390-395. 被引量:2
  • 2黄水龙,王志华.一种通用的可编程双模分频器(英文)[J].北京大学学报(自然科学版),2007,43(1):109-112. 被引量:2
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  • 5Xueyi Yu,Yuanfeng Sun,Woogeun Rhee,et al.A ∑-ΔFractional N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications[J].IEEE Solid State Circuits,2009,44(8):2197-2198.
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  • 7Dehghani R.A 2.5 GHz CMOS Fully Integrated Delta-Sigma Controlled Fractional-N Frequency Synthesizer[C] //Proc IEEEnt Conf VLSI Design,2004,163-167.
  • 8应文荣.小数分频频率合成器的建摸与设计[D].上海:上海交通大学,2012:16-19.
  • 9何素东,吴建辉,周越.ΣΔ调制器的设计方法[J].电子器件,2008,31(2):516-519. 被引量:3
  • 10汤黎明,吴建辉.四阶连续时间正交带通ΣΔ调制器的设计[J].电子器件,2010,33(1):58-61. 被引量:1

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