支持多优先级的高速crossbar调度器的设计与实现

Design and implementation of high-speed crossbar scheduler with multiple priorities

为了在高速交换中提供具有服务质量保证的调度器,提出了基于p-iDRR算法的调度器的FPGA实现方案。通过简化调度流程和使用流水线设计方式,使得调度器简单、高速、硬件易实现,并具有良好的性能。采用X ilinx公司的xc2v3000-6bg728芯片实现了支持2个优先级的crossbar调度器,能够支持16个2.5 Gb/s的高速端口。另外,提出了一种软件仿真和硬件仿真相结合的验证方案,用于调度器功能的验证。

The design scheme of scheduler based on p-IDRR by FPGA was proposed in order to provide schedulers with the quality of service guarantees in high-speed switching. It made the scheduler simple, high-speed and easy to implement by simplifying scheduling processes and using pipe-line method. Furthermore, a high-speed crossbar scheduler was implemented with two priorities by using the chip xc2v3000-6bg728 of Xilinx company. The scheduler can support 16 2.5 Gb/s ports. In addition, a verification method that analyzes results of the both software simulation and the hardware simulation was proposed to verify functions of the scheduler.