DVB-S信道内码解码器的FPGA实现

A FPGA Implementation of Inner Decoder in DVB-S System

采用基于软件流水线的回溯法实现维特比译码中的幸存路径管理,从而有效节省了资源消耗,并提高了译码速度；从DVB-S解码器的整体系统结构考虑,使用一种高效的同步头锁定及内码信息确定的方案。整个设计在Xilinx公司的XC2VP30上实现。

Using trace back algorithm based on software pipelining to implement the survivor path management of Viterbi decoder, resource consumption reduces and decoding speed increases. Considering the architecture of DVB - S decoder, an effective solution is performed to detect the sync-word byte and obtain inner code in- formation. The entire application is designed and synthesized on Xilinx＇s XC2VP30.