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嵌入式DSP处理器的体系结构设计 被引量：2

Design of the embedded DSPs’architecture
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摘要 本文就总线结构、指令系统、存储系统、流水线、寻址方式等几个方面对一个嵌入式DSP处理器μDSP的体系结构设计进行了详细的阐述。 Design of the embedded DSPs＇ architecture was described at this aspects： bus structure, instruction system, memory system, pipeline and addressing mode,etc.
作者 钟冬庆
机构地区 赣南师范学院数学与计算机系
出处 《微计算机信息》 北大核心 2006年第10Z期70-71,172,共3页 Control & Automation
关键词 嵌入式DSP处理器 体系结构设计 Embedded DSPs,Design of architecture
分类号 TP273 [自动化与计算机技术—检测技术与自动化装置]
  • 相关文献

参考文献4

  • 1王小明,毛敏.基于DSP的实时多任务嵌入式系统[J].微计算机信息,2005,21(10Z):22-24. 被引量：5
  • 2Phil Lapsley et.al,DSP Processor Fundamental:Architectures and Features,Berkeley,California:Berkeley Design Technology,Inc,1996
  • 3ADSP-219x/2191 DSP Hardware Reference,Analog Devices Inc,2000
  • 4J L.Hennessy,D A.Patterson 著,计算机体系结构:量化研究方法(第三版).北京:机械工业出版社,2003

二级参考文献2

  • 1TMS320C2812 User Guide,Texas Instruments,2004.
  • 2AT49BVl62 User Guide,Atmel,2004.

共引文献4

同被引文献11

  • 1Lishing Liu, "Partial Address Directory for Cache Access" [A], IEEE Transaction on VLSI Systems, Vol.2, No.2, June.1994
  • 2C. Su, A. Despain, “Cache Design Tradeoffs for Power and Performance Optimization: A Case Study,”[A], International Symposium on Low Power Electronics and Design, pp63-68, 1997
  • 3Brad Calder, Dirk Grunwald, Joel Emer, "Predictive Sequential Associative Cache" [A], the 2nd IEEE International Symposium on High Performance Computer Architecture, San Jose, pp244,Feb.1996
  • 4Rui Min, Zhiyong Xu, Yiming Hu, etc., “Partial Tag Comparison: A New Technology for Power-Efficient Set- Associative Cache Designs” [A], Proceedings of the 17th International Conference on VLSI Design, 2004
  • 5K. Inoue, T. Ishihara, K. Murakami, "Way-Predicting set associative cache for high performance and low energy consumption" [A], International Symposium on Low Power Electronics and Design, pp. 273 - 275, 1999
  • 6Premkishore Shivakumar, Norman P. Jouppi, “CACTI 3.0: An Integrated Cache Timing, Power, and Area Model” [C], Western Research Laboratory, 2001
  • 7R.VK.Pillai,D.AL-Khalili,A.J.AL-Khalili and S.Y.A.Shah. A Low Power Approach to Floating Point Adder Design for DSP Applications.Jounal of VLSI Signal Processing 27,195-213, 2001
  • 8Denzil Fernandes,Vijay Raj,Narsimhan Doriswamy. A Synthesis Tool Based Design of A 111MHz CMOS Floating Point Adder With Built In Testability.IEEE 1993
  • 9D.Narasimhan,D.Fernandes,V.K.Raj,J.Dorenbosch,M.Bowden,V. S.Kapoor A 100 MHz FPGA Based Floating Point Adder.IEEE 1993 0-7803-0826-3/93
  • 10NEIL BURGESS. New Models of Prefix Adder Topologies. Journal of VLSI Signal Processing 40,125-141,2005.

引证文献2

二级引证文献2

微计算机信息
2006年 第10Z期

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