摘要
文章介绍了PowerPC60x处理器的总线接口和操作,详细阐述了60x总线存储器控制器在CPLD上的设计与实现过程。此存储器控制器可提供60x总线与多种类型的SRAM的接口,及与FLASH和I/O的接口,已在嵌入式系统的设计中得到了应用和验证。
The PowerPC 60x microprocessors＇ bus interface and its operation are introduced in the paper. Details of the 60x bus memory controller＇s design and implementation based on CPLD are described. This memory controller can provide interfaces to several types of SRAM, FLASH and I/O. It has been applied and verified in a embedded system.
出处
《微计算机信息》
北大核心
2006年第10Z期79-81,267,共4页
Control & Automation
基金
中国科学院知识创新基金资助项目(KGCX-JG-07)
