摘要
提出了一种基于提升格式,高效、实时实现JPEG2000中9/7双正交离散小波变换虑波器的VLSI结构设计方法。该方法所设计的结构,在保证同样的精度下,大大减少了运算量,整体运算速度高,硬件花费少,存储需求低,硬件利用率达到100%。用Verilog HDL对系统进行了硬件描述,并选用X ilinx公司的xcv50e-cs144-8器件在ISE4.1环境下实现了综合。
A high - efficient, real - time VLSI architecture is p that can perform 9/7 biorthogonal discrete wavelet transform （ DWT ） in JPEG2000. By using this architecture, the numbers of computing are reduced enormously With the same precision , the whole computation speed is high with less hardware cost and the memory requirement is low , lated initially by Matlab, and then is -cs144 -8 under Xilinx＇s ISFA. 1. and it can achieve 100% hardware utilization. The algorithm is simu described and simulated by Verilog HDL. It is synthesized by xcv50e -cs144 -8 under Xilinx＇s ISF4. 1.
出处
《电讯技术》
2006年第5期200-204,共5页
Telecommunication Engineering
