摘要
为了降低系统芯片测试成本,需复用IP的测试电路和测试矢量,过去几年已经涌现了许多新型测试结构。测试包和测试轨由于其结构简单,已经广泛应用于系统芯片的测试方案中。但基于测试包和测试轨的测试调度算法复杂度很高,难以获得测试调度的最优解,从而降低了测试效率。本文提出了基于传递闭合图(Transitive Closure Graph)的测试调度表示法,该表示法符合P-admissible准则,使组合优化算法适用于SoC测试调度问题。最后本文用模拟退火算法来优化测试调度,实验结果表明此算法调度的测试时间要比报道的结果都好。
Many novel testing structures for system-on-a-chip are proposed for decreasing testing cost and facilitating test reuse. For the simplicity of Test Collar and test rail, they are widely used in today's SoC test solutions. But the test scheduling problem of test rail and collar is very complex, and it is hard to get the optimum solution. A novel description of test schedule based on transitive closure graph is proposed in this paper, and it is suitable for combinational optimization. Simulated annealing algorithm is used to get the optimum test solution, and it demonstrates its advantage over other solution published recently in test time.
出处
《电路与系统学报》
CSCD
北大核心
2006年第5期37-43,36,共8页
Journal of Circuits and Systems
基金
国家自然科学基金基于测试压缩和LBIST的系统芯片低成本测试技术研究(90407009)
关键词
系统芯片
可测性设计
模拟退火
system-on-a-chip, design for testing, simulated annealing