基于FFT的两种伪码快速捕获方案的研究与实现

Two Methods of Rapid Code Acquisition Based on FFT

该文提出两种基于FFT的伪码快速捕获方案,一种是基于分数倍采样率转换器的快捕方案;另一种是基于抽取器的快捕方案。两种伪码快捕电路均利用设计复用技术使硬件规模大幅减少;采用并行设计使系统的运算速度大大提高;采用块浮点算法以提高动态范围和运算精度。两种快捕电路均由一块FPGA实现。仿真和测试结果表明,基于分数倍采样率转换器的快捕电路与基于抽取器的快捕电路相比,占用的硬件资源较大,但是捕获精度更高。

Two methods of rapid code acquisition based on FFT are presented, one method is based on fractional multiple sampling rate convertor, and the other is based on decimation. To reduce hardware resource, two rapid code acquisition circuits utilizes duplicate design. Two designs applied parallel pipeline structure to improve the processing speed. Block floating-point arithmetic is used to enhance the dynamic range and computation accuracy. Two designs are implemented with a chip of FPGA respectively, simulation and measurement results show that the rapid code acquisition circuit based on fractional multiple sampling rate convertor costs more hardware resource, but can gain higher acquisition accuracy to be compared with the method based on decimation.