基于FPGA的信道编译码系统设计

FPGA-based Design for Signal Channel Encoding/Decoding System(SCEDS)

论述了在整个无线收发系统中用软件的方法实现信道编译码系统的功能。信道编译码系统包括发射端的信道编码和接收端的信道译码两大部分。本系统的实现过程是:先通过软件编程实现各部分的功能模块,然后编程连接各模块,系统编译仿真通过以后载入FPGA(现场可编程门阵列)芯片,验证结果。实验表明,该系统结果符合了设计的要求。

This project describes the method that implement the signal encoding/decoding system by software in the whole wireless system. This system consists of signal encoding in the sending part and signal decoding in the receiving part. The first step is using software to program and implement every function modules of the system, then program the linking interfaces among these modules to get connection. After getting success in the simulation,load these programmed modules into FPGA chip to implement the function of the encoding/decoding system. The result of testing shows that the performance of SCEDS has satisfied the purpose of design.