期刊文献+

两相邻耦合RC互连的串扰效应及其抑制

Effect and Control of Crosstalk between Two Neighboring Coupled RC Interconnects
下载PDF
导出
摘要 随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。 As development of microelectronic technique, the technology scale is under reducing, IC design has been confronted with the challenge of submicron designs. A series of SI problem should be considered by the designer,the interconnect crosstalk becomes a critical issue to the design. To this question,the paper discusses the harm of crosstalk,analyzes the causes of crosstalk between two neighboring coupled RC interconnects in submicron integrated circuit,and introduces how to get the R and C parameters. Then,sets up the tenth order model of two neighboring parallel long interconnections, and analyzes the factors of cause crosstalk by simulation using the software of Cadence. Based on the simulation get the conclusions of the effective methods to controlling crosstalk.
机构地区 河北工程大学
出处 《现代电子技术》 2006年第21期142-144,共3页 Modern Electronics Technique
关键词 串扰 信号完整性 互连 集成电路 crosstalk signal integrity interconnect IC
  • 相关文献

参考文献8

  • 1Chandrakasan A P,Allmon R,Stratakos A,et al.Design of Portable Systems[A].IEEE CICC[C].San Diego:IEEE.1994:259-266.
  • 2Sakurai T.Closed-form Expressions for Interconnection Delay,Couplingand Crosstalk in VLSIs[J].IEEE Trans.on ED,1993,40(1):118-124.
  • 3Vittal A,Marek-Sadowska M.Crosstalk Reduction for VLSI[J].IEEE Trans.on CAD,1997,15(3):290-298.
  • 4Becer M R,Blaauw D,Zolotov V,et al.Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model[A].DATE[C].Paris:IEEE,2002:456-463.
  • 5Cong J,Zhingang D,Srinivas P V.Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization[A].ASP/DAC[C].Yokohama:IEEE,2001:373-378.
  • 6Becer M R,Blaauw D,Zolotov V,et al.Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model[A].DATE[C].Paris:IEEE,2002:456-463.
  • 7马剑武,陈书明,孙永节.深亚微米集成电路设计中串扰分析与解决方法[J].计算机工程与科学,2005,27(4):102-104. 被引量:3
  • 8Delorme N,Belleville M,et al.Inductance and Capacitance Analytic Formulas for VLSI Interconnects[J].Electronics Letters,1996,32 (11):996-997.

二级参考文献4

  • 1Rajesh Kumar. Interconnect and Noise Immunity Design for the PentiumR 4 Processor[J]. Intel Technology Journal, 1st Quarter[J]. 2001.
  • 2Monterey Design System Corp.White Paper on Signal Integrity[Z]. 2001.
  • 3Wayne W-M Dai. Chip Parasitic Extraction and Signal Integrity Verification[A]. DAC'97[C].1997.
  • 4Ankireddy Nalamalpu, Wayne Burleson. Boosters for Driving Long On-chip Interconnects: Design Issues, Interconnect Synthesis and Comparison with Repeaters[A]. ISPD'01[C]. 2001.

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部