摘要
描述了基于CSA(Current Steer Amplifier)架构的压控振荡(VCO)的锁相环设计和仿真.电路设计基于0.25μm CMOS工艺.SPICE仿真结果显示,锁相环在2.5 V外加电源电压时,工耗为12.5 mW,锁相环锁定时间大约400 ns.
A phase locked loop（PLL） based on VCO with CSA is described. The circuit design is realized in 0.25μm CMOS technology. SPICE simulation with a 2.5 V supply voltage shows that the power consumption is 12.5 mW, and the lock time of the PLL is about 400 ns.
出处
《武汉大学学报（工学版）》
CAS
CSCD
北大核心
2006年第5期102-104,109,共4页
Engineering Journal of Wuhan University
基金
国家自然科学基金资助(编号:50577046)
关键词
锁相环
压控振荡器
CMOS
phase locked loop
voltage controlled oscillator
CMOS
