32位快速乘法器设计

Design of high performance 32 bit multipliers

本文介绍了一种通过符号位扩展,可以分别完成32位有符号/无符号二进制数乘法的高性能乘法器设计。该乘法器采用高基Booth算法,简化部分积的符号扩展,通过采用较之常规Wallace树具有更规则和更简洁的连接复杂度的阵列结构以及一种新型超前进位加法器来进一步提高乘法器的运算速度。整个设计采用4级流水线结构,在FPGA上进行了验证,并成功地应用于时/频联合均衡器工作中。

The design of high performance multiplier which supports both signed and unsigned 32 bit multiplication by an additive sign bit is proposed. Predigest the sign bit spread of partial product by using the high radix Booth algorithm. To improve the speed of the multipliers, a novel tree structure is adopted, which is provided with simpler wring and more regular structure than common Wallace tree. Furthermore, a novel leading carry adder is adopted. The whole design uses the technology of four stage pipelines, and is validated in the FPGA. Finally, it is successfully applied in the frequency-domain equalizer.