一种适合于并行译码的Turbo交织器的设计

A New Interleaver Design Method for Turbo Code Using Parallel Decoding

高数据率的通信系统要求有高吞吐量的译码器,而并行译码是高吞吐量的译码器的一种有效实现方法。对于采用并行译码的Turbo码,交织器的设计是决定其性能和译码器吞吐量的关键因素。本文在A.Giuliett提出的没有读写冲突的并行交织器的设计原则基础上,给出了一种新型的交织器设计方法。该方法在保证Turbo优越性能的前提下,使得高并行度的译码成为可能。译码性能的仿真结果验证了设计方案的良好译码性能,通过FPGA的硬件实现验证了译码器吞吐量的极大提高。该设计方案可用于Beyond3G系统。

High-speed, low latency turbo codes require the parallel decoder architecture, As a key part of the decoder, the interleaver also should have a parallel structure that can avoid collisions in accesses to storage elements, and also keep excellent BER performance. In this paper we propose an interleaver structure that is very suitable for parallelization of turbo decoders, based on the structure of A. Giuliett＇s principle of collision-free interleaver design. It is shown that such an interleaver can be designed to have good BER performance as well. By this structure fast decoders with very low latency can be built, and the throughput of the decoder can be improved by about10 times. This design of interleaver can be used in the Beyond 3G system.