网络层协议处理器的设计与研究

The Design and Research about Protocol Processor at Network layer

吉比特网络下,网络终端CPU处理TCP/IP协议的能力已经成为网络应用的瓶颈。为了使终端用户能充分利用广阔的带宽资源,该文提出了一种硬件实现方法,将原来由软件完成的IP层协议功能完全卸载出来,并通过DMA(直接存储器访问)接口直接进行主存读写,从而减少了CPU的负荷。并且基于FPGA设计流程,通过功能仿真、综合后仿真、布局布线后仿真验证了协议处理器的可行性。该处理器具有灵活的电路接口,所用逻辑资源少,管脚数量少,成本低易于集成,是一种高效的解决方案。

Over Gigabit Ethernet,the terminal cpu that executes the TCP/IP stack software has become the bottleneck. In order that the end-user can take advantage of the vast band resource, this paper presents a design based on hardware to offload the total tasks involved in IP layer which were traditionally processed in software and it can directly read and write main memory through DMA（direct memory access） interface, so that the burden of CPU will be reduced. The feasibility of the design has been proved by functional simulation, post-synthesis simulation and post-place＆route simulation. This processor is a highly efficient solution with flexible circuit interfaces , less logic resources , less base pins, easy access to be integrated at low cost.