多微处理器系统中总线仲裁逻辑的设计

The design of bus arbitrating logic on multiprocessor systems

本文给出了一种多微处理器体系结构,重点讨论了多微处理器间信息交换和仲裁逻辑的实现机制及具体设计步骤,并给出了具体实现的硬件逻辑电路及交换的时序图。实际运行表明:该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点;它完全能满足高性能的测控系统和各种高精度的智能仪器仪表的特殊要求。

The novel way of multiprocessor system architecture is presented in this paper. Message exchanging, bus arbitrating strategy and specific design procedure are discussed in detail among multiprocessor systems. Finally, a specific circuit of hardware and timing diagrams of message exchanging about the bus arbitrating logic are given. Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability. It is fit for various types of monitoring and controlling systems and sophisticated intellectual instrument especially.