高速离散余弦变换VLSI实现的可测性设计

Design for Testability of a Novel High-Speed DCT in VLSI

本文提出了一种离散余弦变换电路VLSI实现的可测试性设计。它采用基于算法结构变换的并行实现,所用乘法的数量大大减少,降低了硬件面积占用和功率消耗。为提高DCT的可靠性,在本设计中加入可测性设计方法,采用一种新的内建自测试(BIST)技术。实验表明该设计对运算器的内部结构和运算速度影响小,并具有较高的故障覆盖率。本文的方法适用于高可靠性要求下的数字信号处理的VLSI实现。

In this paper , a VLSI implementation method of design-for-testability for DCT is presented . The algorithm-architecture transformation can be used to derive efficient DCT implementations where the number of multiplication can be reduced dramatically . It adopt a parallel architecture to reduce hardware overhead and power consumption , To improve the testability of DCT. a novel build-in self-test technique can be adopt in the method of design for testability , The BIST structure has a little influence on the inner multiplier structure and its speed . The test results show that it obtains a high fault coverage , The method of the paper can be used as VLSI realization of digital signal process with high reliability.