摘要
使用抽象状态机模型(ASM)对Verilog的语义进行研究,给出各类赋值语句和延迟/事件控制结构的形式定义。以此为基础与VHDL进行对比,说明各种赋值语句和延迟/事件控制结构向VHDL的转换方法以及二者在转换前后的差异。
Verilog＇s formal semantics using the abstract states machine are studied, and the formal definition of assignment statements and delay/event control mechanism is given. Comparing with Borger＇s definition on VHDL, the key methods on how to translate Verilog description to VHDL are explained. In the end, the simulation differences before and after translation are studied.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2006年第21期1-2,21,共3页
Computer Engineering
基金
国防基础科研基金资助项目
