一种低功耗预比较TLB结构

A Precomparison TLB Structure for Low Power

介绍了一种低功耗TLB结构。这种结构的思想是基于程序局部性原理,结合Block Buffering[1]技术,并对CAM结构进行改造,提出一种预比较TLB结构,实现低功耗的TLB。并且采用Simplescalar 3.0模拟该TLB结构和几种传统的TLB结构的失效率。通过改进的CACTI3[2]模拟结果显示:提出的TLB结构比FA-TLB平均功耗×延迟降低约85%,比Micro-TLB降低80%,比Victim-TLB降低66%,比Bank-TLB降低66%以上。从而,所提出的TLB结构可以达到降低功耗的目的。

A structure of TLB for low power is introduced. The idea of the proposed TLB is based on the spatial locality, which is the result of combining with the block buffering technology and adjustment of the CAM structure. All of these make the TLB for low power. With Simple Scalar 3.0, a simulation of the proposed TLB and some traditional TLB structures were made to observe the miss ratio. The simulation results from the modified CACTI3 show that the proposed TLB structure can reduce power s delay about 85 %, 80%, 66%, and 66%, compared with a FA-TLB, a miero-TLB, a vietim-TLB, and a bank-TLB. Therefore the proposed TLB can achieve low power.