高动态短时突发通信系统数字锁相环设计

Design of DPLL for the High Dynamic and Short-term Burst Communication System

根据实际应用背景给出了一种数字锁相环参数设计方法,并对其捕获性能进行了分析,然后在具体系统中综合考虑载波同步、符号同步与帧同步对本数字锁相环的影响,并以“通过率”来评价其性能。实践表明,该数字锁相环在低信噪比下仍具有良好性能。

This paper gives a method for the design of Digital Phase-Lock Loop （DPLL） according to the background of actual application, and analyses the acquisition performance of DPLL, then considers the influence of Carrier Synchronization, Symbol Synchronization, Frame Synchronization to the DPLL,and finally evaluates its performance with ＂pass ratio＂. It has been proved that the DPLL has a good performance in the low SNR （Signal-to-Noise Ratio） situation.