摘要
论文分析了面向多媒体应用的TTA(TransportTriggeredArchitecture)微处理器的特点和访存要求,提出并设计实现了应用于此款微处理器、采用直接映象规则、写回和按写分配策略的4KB数据Cache,并在全系统环境下对其进行了模拟验证。实验结果说明数据Cache系统在降低命中时间和提高命中率两方面做到了良好的折中,命中时间与芯片流水线处理周期匹配,有效保证了全系统性能的发挥。
The characteristics of Transport Triggered Architecture（TTA） have been analyzed.The excellent process ability of TTA pipeline gave high demands to the data cache,A 4 KB data cache system which used direct mapped principle, write back and write allocate strategies has been proposed and implemented.The data cache combined with the TTA pipeline and other function units compose the whole TTA microprocessor,The microprocessor has been simulated completely with real applicatlons.The implementation results prove that the data cache in TTA microprocessor can achieve excellent trade-off for hit time and hit probability.The hit time can match the pipeline cycle and the high performance of the microprocessor is ensured.
出处
《计算机工程与应用》
CSCD
北大核心
2006年第33期8-10,19,共4页
Computer Engineering and Applications
基金
国家自然科学基金资助项目(90407022)
