DVB-C接收机中的时钟恢复电路设计

Design of Timing Recovery Loop for DVB-C Receiver

论文提出一种DVB-C基带芯片中全数字时钟恢复电路的解决方案。环路为反馈结构,包括插值器、时钟误差检测和环路滤波器三个部分。A/D提供4倍符号率以上的采样率,误差检测采用Gardner算法,并做线性插值。通过调节环路滤波器的增益减小时钟误差抖动,同时提出一种判断环路锁定的检测方法。仿真结果表明,环路能够捕获400ppm的时钟频率误差,支持16-、32-、64-、128-、256-QAM调制方式,提供稳定收敛和优异的性能。

This paper presents an all digital timing recovery loop in a single chip for DVB-C receiver.The loop is a second order phase lock loop,consisting of an interpolator,a timing error detector and a loop fiher.Gardner algorithm and linear interpolation are applied for timing error detector and interpolator.Timing jitter is reduced by using different loop filter gains in acquiring and tracking.A new method for lock detector is also presented.The results of an experimental evaluation are also reported which show that the loop increases the acquisition range to 400 ppm and has accurate estimation of frequency and phase offset.The loop supports 16-,32-,64-, 128-,256-QAM and provides reliable convergence and satisfactory steady-state performance.