摘要
论文研究了RS码的原理和编码器结构,分析讨论了有限域上的乘、加运算及其实现方法,在此基础上基于FPGA设计了RS(255,239)编码器,并用ALTERA公司的FPGA芯片进行了实现,最后给出了结果分析。文章对基于FPGA的纠错码设计有重要意义。
This paper researched on the theory and coder structure of the RS code. The FPGA implementation of RS （255,239） coder based on multiplication and addition in Galois Field is analyzed and discussed. An experimentation has been made using ALTERA＇s FPGA chip. At last, the result comparison and analyzation was given. This paper is very meaningful for the Error-Correcting Codes design based on FPGA.
出处
《信息安全与通信保密》
2006年第12期78-79,82,共3页
Information Security and Communications Privacy
关键词
RS码
FPGA
有限域乘法
RS code
FPGA
multiplication in galois field
