微晶硅薄膜晶体管稳定性研究

Investigation on stability of microcrystalline silicon thin film transistors

对有源区处于结构过渡区的微晶硅底栅薄膜晶体管,测试其偏压衰退特性时,观察到一种“自恢复”的衰退现象.当栅和源漏同时施加10V的偏压时,测试其源-漏电流随时间的变化,发现源-漏电流先衰减、而后又开始恢复上升的反常现象.而当采用栅压为10V、源-漏之间施加零偏压的模式时,源-漏电流随时间呈先是几乎指数式下降、随之是衰退速度减缓的正常衰退趋势.就此现象进行了初步探讨.

Instability of a bottom gate microcrystalline silicon （μc-Si） thin film transistor （TFT）, of which the active layer was deposited by very high frequency-plasma enhanced chemical vapor deposition with silane concentration of 4% diluted by H2 , was measured and compared under two different gate bias stress conditions. A new instability phenomenon of TFT under the voltage bias stress of Vgs = Vds = 10 V was found, where the ratio of the source-drain current of μc-Si TFT to its initial value decreases first, then stays flat for a period of time, then increases. However, under the voltage bias stress of Vgs = 10 V（ Vd8 = 0 V）, the source-drain current of μc-Si TFT decreases as normal exponential decay. Analysis on the change of sub-threshold swing S and threshold voltage Vth, with stress time indicated the recoverable degradation could have resulted from the electron trapping and releasing in μc-Si TFT treated by gate-bias stress with Vds≠ 0.