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Pixel and Column Fixed Pattern Noise Suppression Mechanism in CMOS Image Sensor 被引量:5

Pixel and Column Fixed Pattern Noise Suppression Mechanism in CMOS Image Sensor
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摘要 A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier. A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64 ×64 CIS and successfully fabricated with chartered 0.35μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.
出处 《Transactions of Tianjin University》 EI CAS 2006年第6期442-445,共4页 天津大学学报(英文版)
基金 Supported by National Natural Science Foundation of China (No.60576025).
关键词 CMOS image sensor active pixel fixed pattern noise double sampling offset compensation CMOS图像传感器 像素 固定模式噪声 二次质量检验 偏置补偿
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参考文献8

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