一种改进的高速Reed-Solomon译码算法及其FPGA实现

A modified algorithm for high speed Reed-Solomon decode and its FPGA implementation

对欧几里得译码算法做了进一步的改进,根据新算法在解关键方程模块中采用了新颖的迭代流水线结构以提高电路工作速度、减小电路面积,设计了高速Reed-Solomon译码器.设计的流水线全并行有限域乘法器,有效解决了传统译码器的速度性能瓶颈.在新的译码器架构基础上,设计了译码器的门级电路,用Xilinx的VirtexII XC2V1000进行了实现和仿真,获得了理想的成果.

Reed-Solomon（RS） codes are forward error correct codes which have been widely used in a variety of communication systems and information storages. This paper modifies the extended Euclidean algorithm first. On the basis of the modified algorithm, we have designed the detailed circuit diagram. We use the pipelined recursive structure to solve the key equation of the decoder, which leads to high performance. And we simulate logically the whole RTL level circuit. We design a plpelined fully parallel multiplier to eliminate the speed bottleneck in the conventional decoder. Based on the new RS decode structure, we design and simulate the decoder at the gate level and implement it by the Xilinx Virtexll XC2V1000. Post simulation shows that our decoder performs better in speed and area of the circuit than traditional decoders .