互连线间容性交叉耦合对时序分析的影响

A Study on Timing Analysis for Coupling Interaction Between Interconnects

集成电路的性能越来越受到互连线间寄生效应的影响,特别是引起互连线跳变模式相关延迟的容性交叉耦合已成为影响线路延迟的一个重要因素。为了提高分层的时序分析方法的准确性,文章引入了局部伪交叉耦合和全局伪交叉耦合的概念,提出了一种利用模块间功能关系识别由于模块间连接产生的全局伪交叉耦合的综合分析方法。实验数据证明了考虑全局伪交叉耦合在提高分层时序验证准确性上的价值。

The performance of high-speed VLSI circuits is increasingly limited by interconnect capacitive coupling, Capacitive coupling interaction leading to pattern-dependent delay variation between interconnects contributes to a large portion of the delay of a line. To improve accuracy in hierarchical timing analysis, the notions of local false coupling interaction and global false coupling interaction is introduced, and a comprehensive approach is proposed to identify valid interaction using functional relations considering global false coupling interaction generated by connections between modules. Experiments on benchmark circuits demonstrate the usefulness of considering the global false coupling interaction to reduce the excessive conservatism during hierarchical timing analysis.