系统芯片的可测性设计与测试

On Designing-for-Testability and Testing of System-on-a-Chip

阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。

Challenge in testing System-on-a-Chip（SoC）, compared to test of conventional integrated circuits, are commented. Design-for-testahility（DFT） and model of test infrastructure, such as test access mechanism, core test wrapper, test source and test sink ete,are described. And their configuration characteristics, implemention approach and progresses in academic research are discussed. Specification of IEEE P1500, an international test standard for SoC＇s based on reusable embedded cores is introduced in detail. Finally, suggestions are made on some theoretical problems associated with DFT and SoC test, to which close attention should he payed.