一种10位40 MHz两步式A/D转换器

A 10-Bit 40 MHz Two-Step A/D Converter

提出了一种基于两步转换法(5+6)的高速高精度A/D转换器体系结构,其优点是可以大幅度降低芯片的功耗及面积。采用这种结构,设计了一个10位40 MHz的A/D转换器,并用0.6μm BiCMOS工艺实现。经过电路模拟仿真,在40 MHz转换速率,1 V输入信号(Vp-p),5 V电源电压时,信噪比(SNR)为63.3 dB,积分非线性(INL)和微分非线性(DNL)均小于10位转换器的±0.5 LSB,电源电流为85.4 mA。样品测试结果:SNR为55 dB,INL和DNL小于10位转换器的±1.75 LSB。

A high-speed and high precision BiCMOS ADC architecture based on two-step conversion （5＋6） is proposed, which can significantly reduce the power dissipation and area of the ADC chip. Based on the architecture, a 10-bit 40-MHz A/D converter is designed and implemented in 0. 6 μm BiCMOS technology. Circuit simulation shows that, for 1 V input （Vpp） and 5 V voltage supply, the A/D converter has an SNR of 63.3 dB, both INL and DNL less than ±0. 5 LSB and a current supply of 85.4 mA at 40 MHz sampling rate. Test results of the sample circuit show that an SNR of 55 dB, an INL and DNL less than ±1.75 LSB have been achieved for the converter.