系统中浮点乘累加PE的设计与实现

Design and Implementation of Floating-Point Multiply-Accumulate Processing Element under SMVM System

稀疏矩阵向量乘(Sparse Matrix-Vector Multiply,SMVM),形如Ab=x,在科学计算、信息检索、数据挖掘等领域中都是重要的计算核心之一。稀疏矩阵中非零元素的稀疏性,使得在微处理器上实现该类运算时,存在Cache缺失率高等问题,导致性能并不理想。针对该问题提出了基于FPGA实现SMVM运算系统的新思路,对系统功能进行了软硬件划分,并完成了系统中硬件浮点乘累加处理单元(ProcessingElement,PE)的设计与实现。目标器件为Virtex4LX60,工作频率达到123.6MHz。

Sparse Matrix-Vector Multiply,Ab=x,is one of the important kernels in scientific computatlon,text retrieval and data mining.The sparsity of non-zero elements in sparse matrix results in the high Cache miss ratio when implementing on micro-processors,so the performance is not ideal.This paper presents a novel architecture to realize SMVM system on FPGA ,the system functions are divided into software and hardware.This paper presents the design and implementation of floating point multiply accumulate processing element.The target device is Virtex4 LX60,and the working frequency is 123.6 MHz.