基于BCD码的模10^i相位累加器DDS设计

The DDS Design of Modulus 10 Phase Accumulator Based on BCD Code

为了简化DDS系统频率控制字的计算处理,提出基于BCD码模10i相位累加器的DDS设计方案.详细介绍了BCD码相位累加器的设计以及应用于DDS系统的相关问题.由于BCD码逐位计算需使用同步多时钟系统,其工作速度较慢,所以它适合应用于频率范围在数MHz以下的DDS信号发生器的单片式设计.

In order to simplify the computational processing of the frequency control words of the DDS system, this paper puts forward two designs, both taking advantages of modulus 10 phase accumulator. Merits and drawbacks of these two designs are discussed. In this paper, the design of BCD code phase accumulator and its applications in DDS systems are illustrated in detail. The BCD code needs the synchronous multi-clocks system; therefore, it works step by step at a low speed and can be adapted to the single-chip design of DDS signal generator whose frequency is under 10MHz.