一种新的基于FPGA实现的判决反馈均衡器结构

A New Structure of Adaptive Decision Feedback Equalizer for FPGA Realization

自适应均衡算法是无线通信系统中解决多径效应的主要手段,由于无线通信系统带宽的不断增加,如何提高自适应均衡器的速度是一个非常迫切的问题,而反馈和复杂的矩阵运算会制约使用LMS算法判决反馈均衡器的工作速度的提高.为此,笔者从LMS算法中的梯度运算出发,解决了误差与均衡器输入向量之间的时序对应关系的协调,从而提出了一种适合于FPGA实现的高速判决反馈均衡器结构,最后给出了在FPGA上的具体实现结果,其表明了该算法对于提高判决反馈均衡器的工作速度有显著的效果.

The algorithm for adaptive decision feedback equalization is a general way to solve multipath effect in wireless communication system. With the bandwidth of the wireless communication system increasing continuously, how to improve the adaptive decision feedback equalization＇s speed has become a very imperative problem. However, feedback and complex matrix operation can draw back the speed of using LMS arithmetic to decising feedback equalizer. Availing itself from the grads operation in the LMS arithmetic, the paper harmonizes the chronological correspondence of error and the equalizer＇s import vector so as to bring forward a structure for decising feedback equalizer in high speed which is fit for the realization of FPGA. The paper has also carried out the practical result on the realization of FPGA, which demonstrates that the algorithm has outstanding effect upon improving the speed of decising feedback equalizer.