基于VHDL的I^2C总线IP核的设计

Design of I^2C IP Core Using VHDL

简述了I^2C总线的特点；并详细描述了一种在FPGA中实现I^2C总线IP核的设计方法；最后给出I^2C总线IP核在主模式下的收发数据仿真时序图以及实现结果。

Aider a brief introducing the feature of I^2C, this paper describes the design method of I^2C IP Core with FPGA in detail. Finally, the time sequence diagram of transmitting and receiving data simulation and the result of implementation are given as the master mode of I^2C.