期刊文献+

一种新颖的自适应判决电路

A Novel Adaptive Decision Circuit
下载PDF
导出
摘要 理论推导了等概率二元码判决时误码率和判决电平的关系,推导表明误码率随着判决门限偏离最佳值急剧升高,因而提出了一种新颖的自适应判决电路,可以使判决门限跟随被判决信号的变化自动调整到最佳值.电路采用SM IC 0.35μm CM O S工艺设计,并给出了芯片针对于27MH z无线FSK信号的接收判决这一具体应用的测试结果. The relationship of BER versus decision level of equal probability Binary code was deduced in detail. It indicated that BER will increase drastically when decision level deviates from the optimum decision level. So a novel adaptive decision circuit was proposed which can automatically adjust its decision level to the optimum one. It was implemented in SMIC 0. 35μm CMOS technology and was used in the 27 MHz wireless FSK receiver.
作者 陈浩琼 吴嶽
出处 《南开大学学报(自然科学版)》 CAS CSCD 北大核心 2006年第6期55-58,共4页 Acta Scientiarum Naturalium Universitatis Nankaiensis
基金 天津市重点攻关项目(033187111)
关键词 判决门限 自适应 误码率 二进制频移键控 decision level adaptive BER BFSK
  • 相关文献

参考文献6

  • 1王彦,叶凡,李联,郑增钰.一个面积和功耗优化且适用于10/100 Base-T以太网的CMOS时钟恢复电路[J].Journal of Semiconductors,2003,24(6):643-648. 被引量:4
  • 2Matsumoto Y,Kuriyama T,Inami D,et al.An adaptive decision threshold control of the optical receiver for multigigabit terrestrial DWDM transmission systems[C/OL]//Optical Fiber Communicatiion Conference and Exhibit,2001:TuR2-1-TuR2-3[2003-05-07].http://ieeexplore.ieee.org/ie15/7379/20048/00927381.pdf.
  • 3Bakker Ten,Kun-Yii Tu,Park Y K.Decision threshold based on dynamic offset compensation for burst mode receiver[C/OL]//27th European Conference,2001:222-223[2002-08-07].http://ieeexplore.ieee.org/ie15/774921295/00988892.pdf.
  • 4陈浩琼,李学初,吴岳.一种高性能CMOS单片中频接收机[J].固体电子学研究与进展,2005,25(3):305-309. 被引量:2
  • 5Elhallabi H,Fouzar Y,Sawan M.High Frequency CMOS Gm-C Bandpass Filter With Automatic On-chip Tuning[C/OL]//Proc ICECS'01,2001:823-826[2002-08-07].http://ieeexplore.ieee.org/ie15/7591/20705/00957601.pdf.
  • 6Ramezani L.An adjustable bandwidth analog CMOS Gm-C filter[C/OL].Proc ICECS'03,2003:420-422[2004-06-01].http://ieeexplore.ieee.org/ie15/9125/28926/01301811,pdf.

二级参考文献11

  • 1Motorola, MC3361B datasheet.
  • 2Darabiand Hooman, Abidi Asad. Noise in RF-CMOS mixers: a simple physical model[J]. IEEE J Solid-State Circuits, 2000;35(1):15-25.
  • 3Huang Po-Chiun, Chen Yi-Hui, Lin Chien-Chil, et al. A 2-V CMOS 455 kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier[J]. IEEE J Solid-State Circuits, 2001;36(1):129-132.
  • 4Tanenbaum A S.Computer Networks.Prentice Hall Interna-tional Inc,1996
  • 5Everitt J,Parker J F,Hurst P,et al.A CMOS transceiver for 10-Mb/s and 100-Mb/s ethernet.IEEE J Solid-State Circuits,1998,33(12):2169
  • 6Carrier sense multiple access with collision detection(CS-MA/CD) access method and physical layer specification.ISO/IEC 8802-3,ANSI/IEEE Standard 802.3 4th ed July 7,1993
  • 7Banu M,Dunlop A.A 660Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and Burst-Mode transmission.ISSCC Dig Tech Papers,1993:102
  • 8Chen D L.A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces.IEEE J Solid-State Circuits,1996,31(8):1170
  • 9Anand S B,Razavi B.A CMOS clock recovery circuit for 2.5-Gb/s NRZ data.IEEE J Solid-State Circuits,2001,36(3):432
  • 10Razavi B.Design of analog CMOS integrated circuit.Mc-Graw-Hill,2001:563

共引文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部