期刊文献+

基于内存总线的高性能I/O接口设计

Design of high performance I/O interface based on memory bus
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摘要 提出了将内存总线扩展为面向系统外部设备互连的局部总线的设计概念.为计算机系统增加了一个高性能的I/O接口总线,提高了主机与外部设备间数据传输的性能,增强了计算机作为事务处理主体的能力.通过对内存总线和内存控制器关键技术的分析,给出了基于SDRAM内存总线的内存目标接口(MTI)设计,在功能和逻辑上实现了内存总线和局部总线间的桥接,为基于内存总线的应用设计提供了一种功能完备的接口部件. A design idea which converts the memory bus to a local bus for system peripheral interconnection is presented in this paper. The great effect of the design is that adding a high efficient I/O interface bus to the computer system. Furthermore, the data transfer performance between the host and peripheral is improved, and the event processing ability of the computer is strengthened greatly. Analyzing the key technology of memory bus and memory controller, the detail design of the memory target interface (MTI) is provided based on SDRAM bus, which is used as a bridge between the memory bus and the local bus. MTI provides the full interface functions for all the design of peripheral based on the memory bus.
出处 《哈尔滨工业大学学报》 EI CAS CSCD 北大核心 2006年第11期1935-1938,共4页 Journal of Harbin Institute of Technology
基金 国家高技术研究发展计划资助项目(2002AA104410)
关键词 内存总线 SDRAM 内存控制器 SPD 纠错码 memory bus SDRAM memory controller SPD ECC
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参考文献6

  • 1Intel, Inc. PC SDRAM Specification, Revision 1.7 [ EB/OL]. November 2000. http://www. intel. com/ technology/memory/.
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二级参考文献3

  • 1intel PC SDRAM Serial Presence Detect (SPD) Specification
  • 224C02 datasheet
  • 3MPC8240 Integrated Processor User′s Manual

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